An example of a traditional IC comprised of a core circuit and input/output (I/O) terminals is illustrated by way of example in FIG. 1. The core circuit is typically comprised of several functional blocks. For example, in a multi-output power management IC (PMIC), the core circuit could consist of several linear regulators, various switch-mode DC-DC converters, system control and sequencing circuits, supervisory circuits, etc. Typically, each of the functional blocks in the core circuit has terminals that are routed to the bond pads, located around the perimeter of the IC, which are connected to package pins through wire bonds, as shown by way of example in FIG. 2. Alternatively, Chip-Scale Packaging (CSP) may be used, where a top metal Redistribution Layer (RDL) is used to reposition the I/O terminal locations, and solder bumps or balls are placed on the redistributed I/O pads such that the IC can be flipped over and mounted on a chip carrier laminate substrate. This packaging process is commonly referred to as “flip-chip” technology.
In particular, FIG. 1 shows an example of a traditional IC comprised of a core circuit 101 and I/O terminals 105, and FIG. 2 shows the IC with bond wires 205 connecting bond pads 120 of the IC to package leads 210, which get soldered to a conventional PCB (not shown) according to known techniques. Core circuit 101 is typically comprised of several functional blocks 115. For example, without limitation, in a multi-output PMIC, the core circuit may comprise several linear regulators, various switch-mode DC-DC converters, system control and sequencing circuits, supervisory circuits, etc. Typically, each functional block 115 in core circuit 101 has terminals that are routed to bond pads 120, located around the perimeter of the IC, which are connected to package pins 210 through wire bonds 205, as shown by way of example in FIG. 2. This assembly suffers from parasitics associated with the internal routing from functional blocks 115 in core circuit 101 to I/O terminals 105 and from I/O terminals 105 to the PCB through wire bonds 205 and package leads 210.
Unfortunately, the prior art suffers from parasitic resistance, capacitance, and inductance (parasitics) associated with the internal IC interconnections from the functional blocks in the core to the I/O pads, and from the parasitics related to the wire bonds and package pins, in the case of traditional wire bond type packages. Furthermore, the assembly of the IC in a package with wire bonds and pins unnecessarily wastes space, which is critical in certain space limited applications. In the case of flip-chip CSP, the prior art also suffers from the RDL routing parasitics.
Furthermore, prior art approaches lack the ability to be easily reconfigured or rearranged to create new products or derivative products. For example, adding new functional blocks would require a complete re-layout of the IC in order to fit-in the additional circuitry. Conversely, removing functional blocks is achieved either by keeping the circuitry on the IC and disabling it or deleting the circuitry. In the former case the die size and cost is not optimal, while in the latter case, the IC re-layout time requires additional research and development time and resources, which are very expensive. In both cases, adding or subtracting circuitry to modify existing products or create new ones, adds risk and cost.
In view of the foregoing there is a need for an improved method for developing highly integrated PMICs that reduces unwanted IC-to-PCB (printed circuit board) parasitics, lowers development risk, and allows much shorter IC and system development times compared to previous solutions.
Unless otherwise indicated illustrations in the figures are not necessarily drawn to scale.